2018-02-08 18:04:43 +00:00
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/**
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* \file bn_mul.h
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*
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* \brief Multi-precision integer library
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*/
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/*
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2020-09-05 10:53:20 +00:00
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* Copyright The Mbed TLS Contributors
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2024-01-30 13:09:13 +00:00
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* SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
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2018-02-08 18:04:43 +00:00
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*/
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/*
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* Multiply source vector [s] with b, add result
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* to destination vector [d] and set carry c.
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*
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* Currently supports:
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*
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* . IA-32 (386+) . AMD64 / EM64T
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* . IA-32 (SSE2) . Motorola 68000
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* . PowerPC, 32-bit . MicroBlaze
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* . PowerPC, 64-bit . TriCore
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* . SPARC v8 . ARM v3+
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* . Alpha . MIPS32
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* . C, longlong . C, generic
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*/
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#ifndef MBEDTLS_BN_MUL_H
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#define MBEDTLS_BN_MUL_H
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2023-09-25 03:04:06 +00:00
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#include "mbedtls/build_info.h"
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2019-07-10 14:15:01 +00:00
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2021-12-21 11:54:05 +00:00
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#include "mbedtls/bignum.h"
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2018-02-08 18:04:43 +00:00
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2021-07-20 10:32:46 +00:00
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/*
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* Conversion macros for embedded constants:
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* build lists of mbedtls_mpi_uint's from lists of unsigned char's grouped by 8, 4 or 2
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*/
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#if defined(MBEDTLS_HAVE_INT32)
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2023-04-18 08:38:24 +00:00
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#define MBEDTLS_BYTES_TO_T_UINT_4(a, b, c, d) \
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((mbedtls_mpi_uint) (a) << 0) | \
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((mbedtls_mpi_uint) (b) << 8) | \
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((mbedtls_mpi_uint) (c) << 16) | \
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((mbedtls_mpi_uint) (d) << 24)
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2021-07-20 10:32:46 +00:00
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2023-04-18 08:38:24 +00:00
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#define MBEDTLS_BYTES_TO_T_UINT_2(a, b) \
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MBEDTLS_BYTES_TO_T_UINT_4(a, b, 0, 0)
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2021-07-20 10:32:46 +00:00
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2023-04-18 08:38:24 +00:00
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#define MBEDTLS_BYTES_TO_T_UINT_8(a, b, c, d, e, f, g, h) \
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MBEDTLS_BYTES_TO_T_UINT_4(a, b, c, d), \
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MBEDTLS_BYTES_TO_T_UINT_4(e, f, g, h)
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2021-07-20 10:32:46 +00:00
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#else /* 64-bits */
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2023-04-18 08:38:24 +00:00
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#define MBEDTLS_BYTES_TO_T_UINT_8(a, b, c, d, e, f, g, h) \
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((mbedtls_mpi_uint) (a) << 0) | \
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((mbedtls_mpi_uint) (b) << 8) | \
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((mbedtls_mpi_uint) (c) << 16) | \
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((mbedtls_mpi_uint) (d) << 24) | \
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((mbedtls_mpi_uint) (e) << 32) | \
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((mbedtls_mpi_uint) (f) << 40) | \
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((mbedtls_mpi_uint) (g) << 48) | \
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((mbedtls_mpi_uint) (h) << 56)
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2021-07-20 10:32:46 +00:00
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2023-04-18 08:38:24 +00:00
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#define MBEDTLS_BYTES_TO_T_UINT_4(a, b, c, d) \
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MBEDTLS_BYTES_TO_T_UINT_8(a, b, c, d, 0, 0, 0, 0)
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2021-07-20 10:32:46 +00:00
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2023-04-18 08:38:24 +00:00
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#define MBEDTLS_BYTES_TO_T_UINT_2(a, b) \
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MBEDTLS_BYTES_TO_T_UINT_8(a, b, 0, 0, 0, 0, 0, 0)
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2021-07-20 10:32:46 +00:00
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#endif /* bits in mbedtls_mpi_uint */
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2023-04-18 08:38:24 +00:00
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/* *INDENT-OFF* */
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2018-02-08 18:04:43 +00:00
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#if defined(MBEDTLS_HAVE_ASM)
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/* armcc5 --gnu defines __GNUC__ but doesn't support GNU's extended asm */
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#if defined(__GNUC__) && \
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( !defined(__ARMCC_VERSION) || __ARMCC_VERSION >= 6000000 )
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2018-07-28 09:16:41 +00:00
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2022-12-21 11:05:54 +00:00
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/*
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* GCC < 5.0 treated the x86 ebx (which is used for the GOT) as a
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* fixed reserved register when building as PIC, leading to errors
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* like: bn_mul.h:46:13: error: PIC register clobbered by 'ebx' in 'asm'
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*
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* This is fixed by an improved register allocator in GCC 5+. From the
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* release notes:
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* Register allocation improvements: Reuse of the PIC hard register,
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* instead of using a fixed register, was implemented on x86/x86-64
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* targets. This improves generated PIC code performance as more hard
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* registers can be used.
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*/
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#if defined(__GNUC__) && __GNUC__ < 5 && defined(__PIC__)
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#define MULADDC_CANNOT_USE_EBX
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#endif
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2018-07-28 09:16:41 +00:00
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/*
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* Disable use of the i386 assembly code below if option -O0, to disable all
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* compiler optimisations, is passed, detected with __OPTIMIZE__
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* This is done as the number of registers used in the assembly code doesn't
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* work with the -O0 option.
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*/
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2022-12-21 11:05:54 +00:00
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#if defined(__i386__) && defined(__OPTIMIZE__) && !defined(MULADDC_CANNOT_USE_EBX)
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2018-02-08 18:04:43 +00:00
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2023-09-25 03:04:06 +00:00
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#define MULADDC_X1_INIT \
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{ mbedtls_mpi_uint t; \
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2018-02-08 18:04:43 +00:00
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asm( \
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"movl %%ebx, %0 \n\t" \
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"movl %5, %%esi \n\t" \
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"movl %6, %%edi \n\t" \
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"movl %7, %%ecx \n\t" \
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"movl %8, %%ebx \n\t"
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2023-09-25 03:04:06 +00:00
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#define MULADDC_X1_CORE \
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2018-02-08 18:04:43 +00:00
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"lodsl \n\t" \
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"mull %%ebx \n\t" \
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"addl %%ecx, %%eax \n\t" \
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"adcl $0, %%edx \n\t" \
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"addl (%%edi), %%eax \n\t" \
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"adcl $0, %%edx \n\t" \
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"movl %%edx, %%ecx \n\t" \
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"stosl \n\t"
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2023-09-25 03:04:06 +00:00
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#define MULADDC_X1_STOP \
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"movl %4, %%ebx \n\t" \
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"movl %%ecx, %1 \n\t" \
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"movl %%edi, %2 \n\t" \
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"movl %%esi, %3 \n\t" \
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: "=m" (t), "=m" (c), "=m" (d), "=m" (s) \
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: "m" (t), "m" (s), "m" (d), "m" (c), "m" (b) \
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: "eax", "ebx", "ecx", "edx", "esi", "edi" \
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); }
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2018-02-08 18:04:43 +00:00
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#if defined(MBEDTLS_HAVE_SSE2)
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2023-09-25 03:04:06 +00:00
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#define MULADDC_X8_INIT MULADDC_X1_INIT
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#define MULADDC_X8_CORE \
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2018-02-08 18:04:43 +00:00
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"movd %%ecx, %%mm1 \n\t" \
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"movd %%ebx, %%mm0 \n\t" \
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"movd (%%edi), %%mm3 \n\t" \
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"paddq %%mm3, %%mm1 \n\t" \
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"movd (%%esi), %%mm2 \n\t" \
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"pmuludq %%mm0, %%mm2 \n\t" \
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"movd 4(%%esi), %%mm4 \n\t" \
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"pmuludq %%mm0, %%mm4 \n\t" \
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"movd 8(%%esi), %%mm6 \n\t" \
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"pmuludq %%mm0, %%mm6 \n\t" \
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"movd 12(%%esi), %%mm7 \n\t" \
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"pmuludq %%mm0, %%mm7 \n\t" \
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"paddq %%mm2, %%mm1 \n\t" \
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"movd 4(%%edi), %%mm3 \n\t" \
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"paddq %%mm4, %%mm3 \n\t" \
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"movd 8(%%edi), %%mm5 \n\t" \
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"paddq %%mm6, %%mm5 \n\t" \
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"movd 12(%%edi), %%mm4 \n\t" \
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"paddq %%mm4, %%mm7 \n\t" \
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"movd %%mm1, (%%edi) \n\t" \
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"movd 16(%%esi), %%mm2 \n\t" \
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"pmuludq %%mm0, %%mm2 \n\t" \
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"psrlq $32, %%mm1 \n\t" \
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"movd 20(%%esi), %%mm4 \n\t" \
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"pmuludq %%mm0, %%mm4 \n\t" \
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"paddq %%mm3, %%mm1 \n\t" \
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"movd 24(%%esi), %%mm6 \n\t" \
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"pmuludq %%mm0, %%mm6 \n\t" \
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"movd %%mm1, 4(%%edi) \n\t" \
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"psrlq $32, %%mm1 \n\t" \
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"movd 28(%%esi), %%mm3 \n\t" \
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"pmuludq %%mm0, %%mm3 \n\t" \
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"paddq %%mm5, %%mm1 \n\t" \
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"movd 16(%%edi), %%mm5 \n\t" \
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"paddq %%mm5, %%mm2 \n\t" \
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"movd %%mm1, 8(%%edi) \n\t" \
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"psrlq $32, %%mm1 \n\t" \
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"paddq %%mm7, %%mm1 \n\t" \
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"movd 20(%%edi), %%mm5 \n\t" \
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"paddq %%mm5, %%mm4 \n\t" \
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"movd %%mm1, 12(%%edi) \n\t" \
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"psrlq $32, %%mm1 \n\t" \
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"paddq %%mm2, %%mm1 \n\t" \
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"movd 24(%%edi), %%mm5 \n\t" \
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"paddq %%mm5, %%mm6 \n\t" \
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"movd %%mm1, 16(%%edi) \n\t" \
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"psrlq $32, %%mm1 \n\t" \
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"paddq %%mm4, %%mm1 \n\t" \
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"movd 28(%%edi), %%mm5 \n\t" \
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"paddq %%mm5, %%mm3 \n\t" \
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"movd %%mm1, 20(%%edi) \n\t" \
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"psrlq $32, %%mm1 \n\t" \
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"paddq %%mm6, %%mm1 \n\t" \
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"movd %%mm1, 24(%%edi) \n\t" \
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"psrlq $32, %%mm1 \n\t" \
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"paddq %%mm3, %%mm1 \n\t" \
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"movd %%mm1, 28(%%edi) \n\t" \
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"addl $32, %%edi \n\t" \
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"addl $32, %%esi \n\t" \
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"psrlq $32, %%mm1 \n\t" \
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"movd %%mm1, %%ecx \n\t"
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2023-09-25 03:04:06 +00:00
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#define MULADDC_X8_STOP \
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2018-02-08 18:04:43 +00:00
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"emms \n\t" \
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"movl %4, %%ebx \n\t" \
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"movl %%ecx, %1 \n\t" \
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"movl %%edi, %2 \n\t" \
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"movl %%esi, %3 \n\t" \
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: "=m" (t), "=m" (c), "=m" (d), "=m" (s) \
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: "m" (t), "m" (s), "m" (d), "m" (c), "m" (b) \
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2018-07-28 09:16:41 +00:00
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: "eax", "ebx", "ecx", "edx", "esi", "edi" \
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2023-09-25 03:04:06 +00:00
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); } \
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2018-02-08 18:04:43 +00:00
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#endif /* SSE2 */
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2023-09-25 03:04:06 +00:00
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2018-02-08 18:04:43 +00:00
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#endif /* i386 */
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#if defined(__amd64__) || defined (__x86_64__)
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2023-09-25 03:04:06 +00:00
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#define MULADDC_X1_INIT \
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2018-02-08 18:04:43 +00:00
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asm( \
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2019-02-16 16:19:46 +00:00
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"xorq %%r8, %%r8\n"
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2018-02-08 18:04:43 +00:00
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2023-09-25 03:04:06 +00:00
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#define MULADDC_X1_CORE \
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2019-02-16 16:19:46 +00:00
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"movq (%%rsi), %%rax\n" \
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"mulq %%rbx\n" \
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"addq $8, %%rsi\n" \
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"addq %%rcx, %%rax\n" \
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"movq %%r8, %%rcx\n" \
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"adcq $0, %%rdx\n" \
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"nop \n" \
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"addq %%rax, (%%rdi)\n" \
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"adcq %%rdx, %%rcx\n" \
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"addq $8, %%rdi\n"
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2018-02-08 18:04:43 +00:00
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2023-09-25 03:04:06 +00:00
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#define MULADDC_X1_STOP \
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2021-10-14 09:02:01 +00:00
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: "+c" (c), "+D" (d), "+S" (s), "+m" (*(uint64_t (*)[16]) d) \
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: "b" (b), "m" (*(const uint64_t (*)[16]) s) \
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: "rax", "rdx", "r8" \
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2018-02-08 18:04:43 +00:00
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);
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#endif /* AMD64 */
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2023-09-25 03:04:06 +00:00
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// The following assembly code assumes that a pointer will fit in a 64-bit register
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// (including ILP32 __aarch64__ ABIs such as on watchOS, hence the 2^32 - 1)
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#if defined(__aarch64__) && (UINTPTR_MAX == 0xfffffffful || UINTPTR_MAX == 0xfffffffffffffffful)
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2021-12-21 11:54:05 +00:00
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2023-09-25 03:04:06 +00:00
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/*
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* There are some issues around different compilers requiring different constraint
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* syntax for updating pointers from assembly code (see notes for
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* MBEDTLS_ASM_AARCH64_PTR_CONSTRAINT in common.h), especially on aarch64_32 (aka ILP32).
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*
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* For this reason we cast the pointers to/from uintptr_t here.
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*/
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#define MULADDC_X1_INIT \
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do { uintptr_t muladdc_d = (uintptr_t) d, muladdc_s = (uintptr_t) s; asm(
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2021-12-21 11:54:05 +00:00
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_CORE \
|
|
|
|
|
"ldr x4, [%x2], #8 \n\t" \
|
|
|
|
|
"ldr x5, [%x1] \n\t" \
|
2021-12-21 11:54:05 +00:00
|
|
|
"mul x6, x4, %4 \n\t" \
|
|
|
|
|
"umulh x7, x4, %4 \n\t" \
|
|
|
|
|
"adds x5, x5, x6 \n\t" \
|
|
|
|
|
"adc x7, x7, xzr \n\t" \
|
|
|
|
|
"adds x5, x5, %0 \n\t" \
|
|
|
|
|
"adc %0, x7, xzr \n\t" \
|
2023-09-25 03:04:06 +00:00
|
|
|
"str x5, [%x1], #8 \n\t"
|
2021-12-21 11:54:05 +00:00
|
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|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_STOP \
|
|
|
|
|
: "+r" (c), \
|
|
|
|
|
"+r" (muladdc_d), \
|
|
|
|
|
"+r" (muladdc_s), \
|
|
|
|
|
"+m" (*(uint64_t (*)[16]) d) \
|
2021-12-21 11:54:05 +00:00
|
|
|
: "r" (b), "m" (*(const uint64_t (*)[16]) s) \
|
|
|
|
|
: "x4", "x5", "x6", "x7", "cc" \
|
2023-09-25 03:04:06 +00:00
|
|
|
); d = (mbedtls_mpi_uint *)muladdc_d; s = (mbedtls_mpi_uint *)muladdc_s; } while (0);
|
2021-12-21 11:54:05 +00:00
|
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|
|
|
|
|
|
#endif /* Aarch64 */
|
|
|
|
|
|
2018-02-08 18:04:43 +00:00
|
|
|
#if defined(__mc68020__) || defined(__mcpu32__)
|
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|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_INIT \
|
2018-02-08 18:04:43 +00:00
|
|
|
asm( \
|
|
|
|
|
"movl %3, %%a2 \n\t" \
|
|
|
|
|
"movl %4, %%a3 \n\t" \
|
|
|
|
|
"movl %5, %%d3 \n\t" \
|
|
|
|
|
"movl %6, %%d2 \n\t" \
|
|
|
|
|
"moveq #0, %%d0 \n\t"
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_CORE \
|
2018-02-08 18:04:43 +00:00
|
|
|
"movel %%a2@+, %%d1 \n\t" \
|
|
|
|
|
"mulul %%d2, %%d4:%%d1 \n\t" \
|
|
|
|
|
"addl %%d3, %%d1 \n\t" \
|
|
|
|
|
"addxl %%d0, %%d4 \n\t" \
|
|
|
|
|
"moveq #0, %%d3 \n\t" \
|
|
|
|
|
"addl %%d1, %%a3@+ \n\t" \
|
|
|
|
|
"addxl %%d4, %%d3 \n\t"
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_STOP \
|
2018-02-08 18:04:43 +00:00
|
|
|
"movl %%d3, %0 \n\t" \
|
|
|
|
|
"movl %%a3, %1 \n\t" \
|
|
|
|
|
"movl %%a2, %2 \n\t" \
|
|
|
|
|
: "=m" (c), "=m" (d), "=m" (s) \
|
|
|
|
|
: "m" (s), "m" (d), "m" (c), "m" (b) \
|
|
|
|
|
: "d0", "d1", "d2", "d3", "d4", "a2", "a3" \
|
|
|
|
|
);
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X8_INIT MULADDC_X1_INIT
|
|
|
|
|
|
|
|
|
|
#define MULADDC_X8_CORE \
|
2018-02-08 18:04:43 +00:00
|
|
|
"movel %%a2@+, %%d1 \n\t" \
|
|
|
|
|
"mulul %%d2, %%d4:%%d1 \n\t" \
|
|
|
|
|
"addxl %%d3, %%d1 \n\t" \
|
|
|
|
|
"addxl %%d0, %%d4 \n\t" \
|
|
|
|
|
"addl %%d1, %%a3@+ \n\t" \
|
|
|
|
|
"movel %%a2@+, %%d1 \n\t" \
|
|
|
|
|
"mulul %%d2, %%d3:%%d1 \n\t" \
|
|
|
|
|
"addxl %%d4, %%d1 \n\t" \
|
|
|
|
|
"addxl %%d0, %%d3 \n\t" \
|
|
|
|
|
"addl %%d1, %%a3@+ \n\t" \
|
|
|
|
|
"movel %%a2@+, %%d1 \n\t" \
|
|
|
|
|
"mulul %%d2, %%d4:%%d1 \n\t" \
|
|
|
|
|
"addxl %%d3, %%d1 \n\t" \
|
|
|
|
|
"addxl %%d0, %%d4 \n\t" \
|
|
|
|
|
"addl %%d1, %%a3@+ \n\t" \
|
|
|
|
|
"movel %%a2@+, %%d1 \n\t" \
|
|
|
|
|
"mulul %%d2, %%d3:%%d1 \n\t" \
|
|
|
|
|
"addxl %%d4, %%d1 \n\t" \
|
|
|
|
|
"addxl %%d0, %%d3 \n\t" \
|
|
|
|
|
"addl %%d1, %%a3@+ \n\t" \
|
|
|
|
|
"movel %%a2@+, %%d1 \n\t" \
|
|
|
|
|
"mulul %%d2, %%d4:%%d1 \n\t" \
|
|
|
|
|
"addxl %%d3, %%d1 \n\t" \
|
|
|
|
|
"addxl %%d0, %%d4 \n\t" \
|
|
|
|
|
"addl %%d1, %%a3@+ \n\t" \
|
|
|
|
|
"movel %%a2@+, %%d1 \n\t" \
|
|
|
|
|
"mulul %%d2, %%d3:%%d1 \n\t" \
|
|
|
|
|
"addxl %%d4, %%d1 \n\t" \
|
|
|
|
|
"addxl %%d0, %%d3 \n\t" \
|
|
|
|
|
"addl %%d1, %%a3@+ \n\t" \
|
|
|
|
|
"movel %%a2@+, %%d1 \n\t" \
|
|
|
|
|
"mulul %%d2, %%d4:%%d1 \n\t" \
|
|
|
|
|
"addxl %%d3, %%d1 \n\t" \
|
|
|
|
|
"addxl %%d0, %%d4 \n\t" \
|
|
|
|
|
"addl %%d1, %%a3@+ \n\t" \
|
|
|
|
|
"movel %%a2@+, %%d1 \n\t" \
|
|
|
|
|
"mulul %%d2, %%d3:%%d1 \n\t" \
|
|
|
|
|
"addxl %%d4, %%d1 \n\t" \
|
|
|
|
|
"addxl %%d0, %%d3 \n\t" \
|
|
|
|
|
"addl %%d1, %%a3@+ \n\t" \
|
|
|
|
|
"addxl %%d0, %%d3 \n\t"
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X8_STOP MULADDC_X1_STOP
|
|
|
|
|
|
2018-02-08 18:04:43 +00:00
|
|
|
#endif /* MC68000 */
|
|
|
|
|
|
|
|
|
|
#if defined(__powerpc64__) || defined(__ppc64__)
|
|
|
|
|
|
|
|
|
|
#if defined(__MACH__) && defined(__APPLE__)
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_INIT \
|
2018-02-08 18:04:43 +00:00
|
|
|
asm( \
|
|
|
|
|
"ld r3, %3 \n\t" \
|
|
|
|
|
"ld r4, %4 \n\t" \
|
|
|
|
|
"ld r5, %5 \n\t" \
|
|
|
|
|
"ld r6, %6 \n\t" \
|
|
|
|
|
"addi r3, r3, -8 \n\t" \
|
|
|
|
|
"addi r4, r4, -8 \n\t" \
|
|
|
|
|
"addic r5, r5, 0 \n\t"
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_CORE \
|
2018-02-08 18:04:43 +00:00
|
|
|
"ldu r7, 8(r3) \n\t" \
|
|
|
|
|
"mulld r8, r7, r6 \n\t" \
|
|
|
|
|
"mulhdu r9, r7, r6 \n\t" \
|
|
|
|
|
"adde r8, r8, r5 \n\t" \
|
|
|
|
|
"ld r7, 8(r4) \n\t" \
|
|
|
|
|
"addze r5, r9 \n\t" \
|
|
|
|
|
"addc r8, r8, r7 \n\t" \
|
|
|
|
|
"stdu r8, 8(r4) \n\t"
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_STOP \
|
2018-02-08 18:04:43 +00:00
|
|
|
"addze r5, r5 \n\t" \
|
|
|
|
|
"addi r4, r4, 8 \n\t" \
|
|
|
|
|
"addi r3, r3, 8 \n\t" \
|
|
|
|
|
"std r5, %0 \n\t" \
|
|
|
|
|
"std r4, %1 \n\t" \
|
|
|
|
|
"std r3, %2 \n\t" \
|
|
|
|
|
: "=m" (c), "=m" (d), "=m" (s) \
|
|
|
|
|
: "m" (s), "m" (d), "m" (c), "m" (b) \
|
|
|
|
|
: "r3", "r4", "r5", "r6", "r7", "r8", "r9" \
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#else /* __MACH__ && __APPLE__ */
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_INIT \
|
2018-02-08 18:04:43 +00:00
|
|
|
asm( \
|
|
|
|
|
"ld %%r3, %3 \n\t" \
|
|
|
|
|
"ld %%r4, %4 \n\t" \
|
|
|
|
|
"ld %%r5, %5 \n\t" \
|
|
|
|
|
"ld %%r6, %6 \n\t" \
|
|
|
|
|
"addi %%r3, %%r3, -8 \n\t" \
|
|
|
|
|
"addi %%r4, %%r4, -8 \n\t" \
|
|
|
|
|
"addic %%r5, %%r5, 0 \n\t"
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_CORE \
|
2018-02-08 18:04:43 +00:00
|
|
|
"ldu %%r7, 8(%%r3) \n\t" \
|
|
|
|
|
"mulld %%r8, %%r7, %%r6 \n\t" \
|
|
|
|
|
"mulhdu %%r9, %%r7, %%r6 \n\t" \
|
|
|
|
|
"adde %%r8, %%r8, %%r5 \n\t" \
|
|
|
|
|
"ld %%r7, 8(%%r4) \n\t" \
|
|
|
|
|
"addze %%r5, %%r9 \n\t" \
|
|
|
|
|
"addc %%r8, %%r8, %%r7 \n\t" \
|
|
|
|
|
"stdu %%r8, 8(%%r4) \n\t"
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_STOP \
|
2018-02-08 18:04:43 +00:00
|
|
|
"addze %%r5, %%r5 \n\t" \
|
|
|
|
|
"addi %%r4, %%r4, 8 \n\t" \
|
|
|
|
|
"addi %%r3, %%r3, 8 \n\t" \
|
|
|
|
|
"std %%r5, %0 \n\t" \
|
|
|
|
|
"std %%r4, %1 \n\t" \
|
|
|
|
|
"std %%r3, %2 \n\t" \
|
|
|
|
|
: "=m" (c), "=m" (d), "=m" (s) \
|
|
|
|
|
: "m" (s), "m" (d), "m" (c), "m" (b) \
|
|
|
|
|
: "r3", "r4", "r5", "r6", "r7", "r8", "r9" \
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
#endif /* __MACH__ && __APPLE__ */
|
|
|
|
|
|
|
|
|
|
#elif defined(__powerpc__) || defined(__ppc__) /* end PPC64/begin PPC32 */
|
|
|
|
|
|
|
|
|
|
#if defined(__MACH__) && defined(__APPLE__)
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_INIT \
|
2018-02-08 18:04:43 +00:00
|
|
|
asm( \
|
|
|
|
|
"lwz r3, %3 \n\t" \
|
|
|
|
|
"lwz r4, %4 \n\t" \
|
|
|
|
|
"lwz r5, %5 \n\t" \
|
|
|
|
|
"lwz r6, %6 \n\t" \
|
|
|
|
|
"addi r3, r3, -4 \n\t" \
|
|
|
|
|
"addi r4, r4, -4 \n\t" \
|
|
|
|
|
"addic r5, r5, 0 \n\t"
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_CORE \
|
2018-02-08 18:04:43 +00:00
|
|
|
"lwzu r7, 4(r3) \n\t" \
|
|
|
|
|
"mullw r8, r7, r6 \n\t" \
|
|
|
|
|
"mulhwu r9, r7, r6 \n\t" \
|
|
|
|
|
"adde r8, r8, r5 \n\t" \
|
|
|
|
|
"lwz r7, 4(r4) \n\t" \
|
|
|
|
|
"addze r5, r9 \n\t" \
|
|
|
|
|
"addc r8, r8, r7 \n\t" \
|
|
|
|
|
"stwu r8, 4(r4) \n\t"
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_STOP \
|
2018-02-08 18:04:43 +00:00
|
|
|
"addze r5, r5 \n\t" \
|
|
|
|
|
"addi r4, r4, 4 \n\t" \
|
|
|
|
|
"addi r3, r3, 4 \n\t" \
|
|
|
|
|
"stw r5, %0 \n\t" \
|
|
|
|
|
"stw r4, %1 \n\t" \
|
|
|
|
|
"stw r3, %2 \n\t" \
|
|
|
|
|
: "=m" (c), "=m" (d), "=m" (s) \
|
|
|
|
|
: "m" (s), "m" (d), "m" (c), "m" (b) \
|
|
|
|
|
: "r3", "r4", "r5", "r6", "r7", "r8", "r9" \
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
#else /* __MACH__ && __APPLE__ */
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_INIT \
|
2018-02-08 18:04:43 +00:00
|
|
|
asm( \
|
|
|
|
|
"lwz %%r3, %3 \n\t" \
|
|
|
|
|
"lwz %%r4, %4 \n\t" \
|
|
|
|
|
"lwz %%r5, %5 \n\t" \
|
|
|
|
|
"lwz %%r6, %6 \n\t" \
|
|
|
|
|
"addi %%r3, %%r3, -4 \n\t" \
|
|
|
|
|
"addi %%r4, %%r4, -4 \n\t" \
|
|
|
|
|
"addic %%r5, %%r5, 0 \n\t"
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_CORE \
|
2018-02-08 18:04:43 +00:00
|
|
|
"lwzu %%r7, 4(%%r3) \n\t" \
|
|
|
|
|
"mullw %%r8, %%r7, %%r6 \n\t" \
|
|
|
|
|
"mulhwu %%r9, %%r7, %%r6 \n\t" \
|
|
|
|
|
"adde %%r8, %%r8, %%r5 \n\t" \
|
|
|
|
|
"lwz %%r7, 4(%%r4) \n\t" \
|
|
|
|
|
"addze %%r5, %%r9 \n\t" \
|
|
|
|
|
"addc %%r8, %%r8, %%r7 \n\t" \
|
|
|
|
|
"stwu %%r8, 4(%%r4) \n\t"
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_STOP \
|
2018-02-08 18:04:43 +00:00
|
|
|
"addze %%r5, %%r5 \n\t" \
|
|
|
|
|
"addi %%r4, %%r4, 4 \n\t" \
|
|
|
|
|
"addi %%r3, %%r3, 4 \n\t" \
|
|
|
|
|
"stw %%r5, %0 \n\t" \
|
|
|
|
|
"stw %%r4, %1 \n\t" \
|
|
|
|
|
"stw %%r3, %2 \n\t" \
|
|
|
|
|
: "=m" (c), "=m" (d), "=m" (s) \
|
|
|
|
|
: "m" (s), "m" (d), "m" (c), "m" (b) \
|
|
|
|
|
: "r3", "r4", "r5", "r6", "r7", "r8", "r9" \
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
#endif /* __MACH__ && __APPLE__ */
|
|
|
|
|
|
|
|
|
|
#endif /* PPC32 */
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The Sparc(64) assembly is reported to be broken.
|
|
|
|
|
* Disable it for now, until we're able to fix it.
|
|
|
|
|
*/
|
|
|
|
|
#if 0 && defined(__sparc__)
|
|
|
|
|
#if defined(__sparc64__)
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_INIT \
|
2018-02-08 18:04:43 +00:00
|
|
|
asm( \
|
|
|
|
|
"ldx %3, %%o0 \n\t" \
|
|
|
|
|
"ldx %4, %%o1 \n\t" \
|
|
|
|
|
"ld %5, %%o2 \n\t" \
|
|
|
|
|
"ld %6, %%o3 \n\t"
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_CORE \
|
2018-02-08 18:04:43 +00:00
|
|
|
"ld [%%o0], %%o4 \n\t" \
|
|
|
|
|
"inc 4, %%o0 \n\t" \
|
|
|
|
|
"ld [%%o1], %%o5 \n\t" \
|
|
|
|
|
"umul %%o3, %%o4, %%o4 \n\t" \
|
|
|
|
|
"addcc %%o4, %%o2, %%o4 \n\t" \
|
|
|
|
|
"rd %%y, %%g1 \n\t" \
|
|
|
|
|
"addx %%g1, 0, %%g1 \n\t" \
|
|
|
|
|
"addcc %%o4, %%o5, %%o4 \n\t" \
|
|
|
|
|
"st %%o4, [%%o1] \n\t" \
|
|
|
|
|
"addx %%g1, 0, %%o2 \n\t" \
|
|
|
|
|
"inc 4, %%o1 \n\t"
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_STOP \
|
2018-02-08 18:04:43 +00:00
|
|
|
"st %%o2, %0 \n\t" \
|
|
|
|
|
"stx %%o1, %1 \n\t" \
|
|
|
|
|
"stx %%o0, %2 \n\t" \
|
|
|
|
|
: "=m" (c), "=m" (d), "=m" (s) \
|
|
|
|
|
: "m" (s), "m" (d), "m" (c), "m" (b) \
|
|
|
|
|
: "g1", "o0", "o1", "o2", "o3", "o4", \
|
|
|
|
|
"o5" \
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
#else /* __sparc64__ */
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_INIT \
|
2018-02-08 18:04:43 +00:00
|
|
|
asm( \
|
|
|
|
|
"ld %3, %%o0 \n\t" \
|
|
|
|
|
"ld %4, %%o1 \n\t" \
|
|
|
|
|
"ld %5, %%o2 \n\t" \
|
|
|
|
|
"ld %6, %%o3 \n\t"
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_CORE \
|
2018-02-08 18:04:43 +00:00
|
|
|
"ld [%%o0], %%o4 \n\t" \
|
|
|
|
|
"inc 4, %%o0 \n\t" \
|
|
|
|
|
"ld [%%o1], %%o5 \n\t" \
|
|
|
|
|
"umul %%o3, %%o4, %%o4 \n\t" \
|
|
|
|
|
"addcc %%o4, %%o2, %%o4 \n\t" \
|
|
|
|
|
"rd %%y, %%g1 \n\t" \
|
|
|
|
|
"addx %%g1, 0, %%g1 \n\t" \
|
|
|
|
|
"addcc %%o4, %%o5, %%o4 \n\t" \
|
|
|
|
|
"st %%o4, [%%o1] \n\t" \
|
|
|
|
|
"addx %%g1, 0, %%o2 \n\t" \
|
|
|
|
|
"inc 4, %%o1 \n\t"
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_STOP \
|
2018-02-08 18:04:43 +00:00
|
|
|
"st %%o2, %0 \n\t" \
|
|
|
|
|
"st %%o1, %1 \n\t" \
|
|
|
|
|
"st %%o0, %2 \n\t" \
|
|
|
|
|
: "=m" (c), "=m" (d), "=m" (s) \
|
|
|
|
|
: "m" (s), "m" (d), "m" (c), "m" (b) \
|
|
|
|
|
: "g1", "o0", "o1", "o2", "o3", "o4", \
|
|
|
|
|
"o5" \
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
#endif /* __sparc64__ */
|
|
|
|
|
#endif /* __sparc__ */
|
|
|
|
|
|
|
|
|
|
#if defined(__microblaze__) || defined(microblaze)
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_INIT \
|
2018-02-08 18:04:43 +00:00
|
|
|
asm( \
|
|
|
|
|
"lwi r3, %3 \n\t" \
|
|
|
|
|
"lwi r4, %4 \n\t" \
|
|
|
|
|
"lwi r5, %5 \n\t" \
|
|
|
|
|
"lwi r6, %6 \n\t" \
|
|
|
|
|
"andi r7, r6, 0xffff \n\t" \
|
|
|
|
|
"bsrli r6, r6, 16 \n\t"
|
|
|
|
|
|
2022-12-21 11:05:54 +00:00
|
|
|
#if(__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__)
|
|
|
|
|
#define MULADDC_LHUI \
|
|
|
|
|
"lhui r9, r3, 0 \n\t" \
|
|
|
|
|
"addi r3, r3, 2 \n\t" \
|
|
|
|
|
"lhui r8, r3, 0 \n\t"
|
|
|
|
|
#else
|
|
|
|
|
#define MULADDC_LHUI \
|
2018-02-08 18:04:43 +00:00
|
|
|
"lhui r8, r3, 0 \n\t" \
|
|
|
|
|
"addi r3, r3, 2 \n\t" \
|
2022-12-21 11:05:54 +00:00
|
|
|
"lhui r9, r3, 0 \n\t"
|
|
|
|
|
#endif
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_CORE \
|
2022-12-21 11:05:54 +00:00
|
|
|
MULADDC_LHUI \
|
2018-02-08 18:04:43 +00:00
|
|
|
"addi r3, r3, 2 \n\t" \
|
|
|
|
|
"mul r10, r9, r6 \n\t" \
|
|
|
|
|
"mul r11, r8, r7 \n\t" \
|
|
|
|
|
"mul r12, r9, r7 \n\t" \
|
|
|
|
|
"mul r13, r8, r6 \n\t" \
|
|
|
|
|
"bsrli r8, r10, 16 \n\t" \
|
|
|
|
|
"bsrli r9, r11, 16 \n\t" \
|
|
|
|
|
"add r13, r13, r8 \n\t" \
|
|
|
|
|
"add r13, r13, r9 \n\t" \
|
|
|
|
|
"bslli r10, r10, 16 \n\t" \
|
|
|
|
|
"bslli r11, r11, 16 \n\t" \
|
|
|
|
|
"add r12, r12, r10 \n\t" \
|
|
|
|
|
"addc r13, r13, r0 \n\t" \
|
|
|
|
|
"add r12, r12, r11 \n\t" \
|
|
|
|
|
"addc r13, r13, r0 \n\t" \
|
|
|
|
|
"lwi r10, r4, 0 \n\t" \
|
|
|
|
|
"add r12, r12, r10 \n\t" \
|
|
|
|
|
"addc r13, r13, r0 \n\t" \
|
|
|
|
|
"add r12, r12, r5 \n\t" \
|
|
|
|
|
"addc r5, r13, r0 \n\t" \
|
|
|
|
|
"swi r12, r4, 0 \n\t" \
|
|
|
|
|
"addi r4, r4, 4 \n\t"
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_STOP \
|
2018-02-08 18:04:43 +00:00
|
|
|
"swi r5, %0 \n\t" \
|
|
|
|
|
"swi r4, %1 \n\t" \
|
|
|
|
|
"swi r3, %2 \n\t" \
|
|
|
|
|
: "=m" (c), "=m" (d), "=m" (s) \
|
|
|
|
|
: "m" (s), "m" (d), "m" (c), "m" (b) \
|
2018-06-07 14:25:01 +00:00
|
|
|
: "r3", "r4", "r5", "r6", "r7", "r8", \
|
2018-02-08 18:04:43 +00:00
|
|
|
"r9", "r10", "r11", "r12", "r13" \
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
#endif /* MicroBlaze */
|
|
|
|
|
|
|
|
|
|
#if defined(__tricore__)
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_INIT \
|
2018-02-08 18:04:43 +00:00
|
|
|
asm( \
|
|
|
|
|
"ld.a %%a2, %3 \n\t" \
|
|
|
|
|
"ld.a %%a3, %4 \n\t" \
|
|
|
|
|
"ld.w %%d4, %5 \n\t" \
|
|
|
|
|
"ld.w %%d1, %6 \n\t" \
|
|
|
|
|
"xor %%d5, %%d5 \n\t"
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_CORE \
|
2018-02-08 18:04:43 +00:00
|
|
|
"ld.w %%d0, [%%a2+] \n\t" \
|
|
|
|
|
"madd.u %%e2, %%e4, %%d0, %%d1 \n\t" \
|
|
|
|
|
"ld.w %%d0, [%%a3] \n\t" \
|
|
|
|
|
"addx %%d2, %%d2, %%d0 \n\t" \
|
|
|
|
|
"addc %%d3, %%d3, 0 \n\t" \
|
|
|
|
|
"mov %%d4, %%d3 \n\t" \
|
|
|
|
|
"st.w [%%a3+], %%d2 \n\t"
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_STOP \
|
2018-02-08 18:04:43 +00:00
|
|
|
"st.w %0, %%d4 \n\t" \
|
|
|
|
|
"st.a %1, %%a3 \n\t" \
|
|
|
|
|
"st.a %2, %%a2 \n\t" \
|
|
|
|
|
: "=m" (c), "=m" (d), "=m" (s) \
|
|
|
|
|
: "m" (s), "m" (d), "m" (c), "m" (b) \
|
|
|
|
|
: "d0", "d1", "e2", "d4", "a2", "a3" \
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
#endif /* TriCore */
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#if defined(__arm__)
|
|
|
|
|
|
|
|
|
|
#if defined(__thumb__) && !defined(__thumb2__)
|
|
|
|
|
#if defined(MBEDTLS_COMPILER_IS_GCC)
|
|
|
|
|
/*
|
|
|
|
|
* Thumb 1 ISA. This code path has only been tested successfully on gcc;
|
|
|
|
|
* it does not compile on clang or armclang.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#if !defined(__OPTIMIZE__) && defined(__GNUC__)
|
2018-02-08 18:04:43 +00:00
|
|
|
/*
|
2019-02-16 16:19:46 +00:00
|
|
|
* Note, gcc -O0 by default uses r7 for the frame pointer, so it complains about
|
|
|
|
|
* our use of r7 below, unless -fomit-frame-pointer is passed.
|
2018-02-08 18:04:43 +00:00
|
|
|
*
|
|
|
|
|
* On the other hand, -fomit-frame-pointer is implied by any -Ox options with
|
|
|
|
|
* x !=0, which we can detect using __OPTIMIZE__ (which is also defined by
|
|
|
|
|
* clang and armcc5 under the same conditions).
|
|
|
|
|
*
|
2023-09-25 03:04:06 +00:00
|
|
|
* If gcc needs to use r7, we use r1 as a scratch register and have a few extra
|
|
|
|
|
* instructions to preserve/restore it; otherwise, we can use r7 and avoid
|
|
|
|
|
* the preserve/restore overhead.
|
2018-02-08 18:04:43 +00:00
|
|
|
*/
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_SCRATCH "RS .req r1 \n\t"
|
|
|
|
|
#define MULADDC_PRESERVE_SCRATCH "mov r10, r1 \n\t"
|
|
|
|
|
#define MULADDC_RESTORE_SCRATCH "mov r1, r10 \n\t"
|
|
|
|
|
#define MULADDC_SCRATCH_CLOBBER "r10"
|
|
|
|
|
#else /* !defined(__OPTIMIZE__) && defined(__GNUC__) */
|
|
|
|
|
#define MULADDC_SCRATCH "RS .req r7 \n\t"
|
|
|
|
|
#define MULADDC_PRESERVE_SCRATCH ""
|
|
|
|
|
#define MULADDC_RESTORE_SCRATCH ""
|
|
|
|
|
#define MULADDC_SCRATCH_CLOBBER "r7"
|
|
|
|
|
#endif /* !defined(__OPTIMIZE__) && defined(__GNUC__) */
|
|
|
|
|
|
|
|
|
|
#define MULADDC_X1_INIT \
|
2018-02-08 18:04:43 +00:00
|
|
|
asm( \
|
2023-09-25 03:04:06 +00:00
|
|
|
MULADDC_SCRATCH \
|
2018-02-08 18:04:43 +00:00
|
|
|
"ldr r0, %3 \n\t" \
|
|
|
|
|
"ldr r1, %4 \n\t" \
|
|
|
|
|
"ldr r2, %5 \n\t" \
|
|
|
|
|
"ldr r3, %6 \n\t" \
|
2023-09-25 03:04:06 +00:00
|
|
|
"lsr r4, r3, #16 \n\t" \
|
|
|
|
|
"mov r9, r4 \n\t" \
|
|
|
|
|
"lsl r4, r3, #16 \n\t" \
|
|
|
|
|
"lsr r4, r4, #16 \n\t" \
|
|
|
|
|
"mov r8, r4 \n\t" \
|
|
|
|
|
|
2018-02-08 18:04:43 +00:00
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_CORE \
|
|
|
|
|
MULADDC_PRESERVE_SCRATCH \
|
2018-02-08 18:04:43 +00:00
|
|
|
"ldmia r0!, {r6} \n\t" \
|
2023-09-25 03:04:06 +00:00
|
|
|
"lsr RS, r6, #16 \n\t" \
|
2018-02-08 18:04:43 +00:00
|
|
|
"lsl r6, r6, #16 \n\t" \
|
|
|
|
|
"lsr r6, r6, #16 \n\t" \
|
|
|
|
|
"mov r4, r8 \n\t" \
|
|
|
|
|
"mul r4, r6 \n\t" \
|
|
|
|
|
"mov r3, r9 \n\t" \
|
|
|
|
|
"mul r6, r3 \n\t" \
|
|
|
|
|
"mov r5, r9 \n\t" \
|
2023-09-25 03:04:06 +00:00
|
|
|
"mul r5, RS \n\t" \
|
2018-02-08 18:04:43 +00:00
|
|
|
"mov r3, r8 \n\t" \
|
2023-09-25 03:04:06 +00:00
|
|
|
"mul RS, r3 \n\t" \
|
2018-02-08 18:04:43 +00:00
|
|
|
"lsr r3, r6, #16 \n\t" \
|
|
|
|
|
"add r5, r5, r3 \n\t" \
|
2023-09-25 03:04:06 +00:00
|
|
|
"lsr r3, RS, #16 \n\t" \
|
2018-02-08 18:04:43 +00:00
|
|
|
"add r5, r5, r3 \n\t" \
|
|
|
|
|
"add r4, r4, r2 \n\t" \
|
|
|
|
|
"mov r2, #0 \n\t" \
|
|
|
|
|
"adc r5, r2 \n\t" \
|
|
|
|
|
"lsl r3, r6, #16 \n\t" \
|
|
|
|
|
"add r4, r4, r3 \n\t" \
|
|
|
|
|
"adc r5, r2 \n\t" \
|
2023-09-25 03:04:06 +00:00
|
|
|
"lsl r3, RS, #16 \n\t" \
|
2018-02-08 18:04:43 +00:00
|
|
|
"add r4, r4, r3 \n\t" \
|
|
|
|
|
"adc r5, r2 \n\t" \
|
2023-09-25 03:04:06 +00:00
|
|
|
MULADDC_RESTORE_SCRATCH \
|
2018-02-08 18:04:43 +00:00
|
|
|
"ldr r3, [r1] \n\t" \
|
|
|
|
|
"add r4, r4, r3 \n\t" \
|
|
|
|
|
"adc r2, r5 \n\t" \
|
|
|
|
|
"stmia r1!, {r4} \n\t"
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_STOP \
|
2018-02-08 18:04:43 +00:00
|
|
|
"str r2, %0 \n\t" \
|
|
|
|
|
"str r1, %1 \n\t" \
|
|
|
|
|
"str r0, %2 \n\t" \
|
|
|
|
|
: "=m" (c), "=m" (d), "=m" (s) \
|
|
|
|
|
: "m" (s), "m" (d), "m" (c), "m" (b) \
|
|
|
|
|
: "r0", "r1", "r2", "r3", "r4", "r5", \
|
2023-09-25 03:04:06 +00:00
|
|
|
"r6", MULADDC_SCRATCH_CLOBBER, "r8", "r9", "cc" \
|
2018-02-08 18:04:43 +00:00
|
|
|
);
|
2023-09-25 03:04:06 +00:00
|
|
|
#endif /* !defined(__ARMCC_VERSION) && !defined(__clang__) */
|
2023-08-04 16:09:03 +00:00
|
|
|
|
2019-11-12 07:55:43 +00:00
|
|
|
#elif (__ARM_ARCH >= 6) && \
|
|
|
|
|
defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)
|
2023-09-25 03:04:06 +00:00
|
|
|
/* Armv6-M (or later) with DSP Instruction Set Extensions.
|
|
|
|
|
* Requires support for either Thumb 2 or Arm ISA.
|
|
|
|
|
*/
|
2019-02-16 16:19:46 +00:00
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_INIT \
|
|
|
|
|
{ \
|
|
|
|
|
mbedtls_mpi_uint tmp_a, tmp_b; \
|
|
|
|
|
asm volatile (
|
|
|
|
|
|
|
|
|
|
#define MULADDC_X1_CORE \
|
|
|
|
|
".p2align 2 \n\t" \
|
|
|
|
|
"ldr %[a], [%[in]], #4 \n\t" \
|
|
|
|
|
"ldr %[b], [%[acc]] \n\t" \
|
|
|
|
|
"umaal %[b], %[carry], %[scalar], %[a] \n\t" \
|
|
|
|
|
"str %[b], [%[acc]], #4 \n\t"
|
|
|
|
|
|
|
|
|
|
#define MULADDC_X1_STOP \
|
|
|
|
|
: [a] "=&r" (tmp_a), \
|
|
|
|
|
[b] "=&r" (tmp_b), \
|
|
|
|
|
[in] "+r" (s), \
|
|
|
|
|
[acc] "+r" (d), \
|
|
|
|
|
[carry] "+l" (c) \
|
|
|
|
|
: [scalar] "r" (b) \
|
|
|
|
|
: "memory" \
|
|
|
|
|
); \
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#define MULADDC_X2_INIT \
|
|
|
|
|
{ \
|
|
|
|
|
mbedtls_mpi_uint tmp_a0, tmp_b0; \
|
|
|
|
|
mbedtls_mpi_uint tmp_a1, tmp_b1; \
|
|
|
|
|
asm volatile (
|
|
|
|
|
|
|
|
|
|
/* - Make sure loop is 4-byte aligned to avoid stalls
|
|
|
|
|
* upon repeated non-word aligned instructions in
|
|
|
|
|
* some microarchitectures.
|
|
|
|
|
* - Don't use ldm with post-increment or back-to-back
|
|
|
|
|
* loads with post-increment and same address register
|
|
|
|
|
* to avoid stalls on some microarchitectures.
|
|
|
|
|
* - Bunch loads and stores to reduce latency on some
|
|
|
|
|
* microarchitectures. E.g., on Cortex-M4, the first
|
|
|
|
|
* in a series of load/store operations has latency
|
|
|
|
|
* 2 cycles, while subsequent loads/stores are single-cycle. */
|
|
|
|
|
#define MULADDC_X2_CORE \
|
|
|
|
|
".p2align 2 \n\t" \
|
|
|
|
|
"ldr %[a0], [%[in]], #+8 \n\t" \
|
|
|
|
|
"ldr %[b0], [%[acc]], #+8 \n\t" \
|
|
|
|
|
"ldr %[a1], [%[in], #-4] \n\t" \
|
|
|
|
|
"ldr %[b1], [%[acc], #-4] \n\t" \
|
|
|
|
|
"umaal %[b0], %[carry], %[scalar], %[a0] \n\t" \
|
|
|
|
|
"umaal %[b1], %[carry], %[scalar], %[a1] \n\t" \
|
|
|
|
|
"str %[b0], [%[acc], #-8] \n\t" \
|
|
|
|
|
"str %[b1], [%[acc], #-4] \n\t"
|
|
|
|
|
|
|
|
|
|
#define MULADDC_X2_STOP \
|
|
|
|
|
: [a0] "=&r" (tmp_a0), \
|
|
|
|
|
[b0] "=&r" (tmp_b0), \
|
|
|
|
|
[a1] "=&r" (tmp_a1), \
|
|
|
|
|
[b1] "=&r" (tmp_b1), \
|
|
|
|
|
[in] "+r" (s), \
|
|
|
|
|
[acc] "+r" (d), \
|
|
|
|
|
[carry] "+l" (c) \
|
|
|
|
|
: [scalar] "r" (b) \
|
|
|
|
|
: "memory" \
|
|
|
|
|
); \
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#else /* Thumb 2 or Arm ISA, without DSP extensions */
|
|
|
|
|
|
|
|
|
|
#define MULADDC_X1_INIT \
|
2018-02-08 18:04:43 +00:00
|
|
|
asm( \
|
|
|
|
|
"ldr r0, %3 \n\t" \
|
|
|
|
|
"ldr r1, %4 \n\t" \
|
|
|
|
|
"ldr r2, %5 \n\t" \
|
|
|
|
|
"ldr r3, %6 \n\t"
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_CORE \
|
2018-02-08 18:04:43 +00:00
|
|
|
"ldr r4, [r0], #4 \n\t" \
|
|
|
|
|
"mov r5, #0 \n\t" \
|
|
|
|
|
"ldr r6, [r1] \n\t" \
|
|
|
|
|
"umlal r2, r5, r3, r4 \n\t" \
|
2023-09-25 03:04:06 +00:00
|
|
|
"adds r4, r6, r2 \n\t" \
|
2018-02-08 18:04:43 +00:00
|
|
|
"adc r2, r5, #0 \n\t" \
|
2023-09-25 03:04:06 +00:00
|
|
|
"str r4, [r1], #4 \n\t"
|
2018-02-08 18:04:43 +00:00
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_STOP \
|
2018-02-08 18:04:43 +00:00
|
|
|
"str r2, %0 \n\t" \
|
|
|
|
|
"str r1, %1 \n\t" \
|
|
|
|
|
"str r0, %2 \n\t" \
|
|
|
|
|
: "=m" (c), "=m" (d), "=m" (s) \
|
|
|
|
|
: "m" (s), "m" (d), "m" (c), "m" (b) \
|
|
|
|
|
: "r0", "r1", "r2", "r3", "r4", "r5", \
|
2023-09-25 03:04:06 +00:00
|
|
|
"r6", "cc" \
|
2018-02-08 18:04:43 +00:00
|
|
|
);
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#endif /* ISA codepath selection */
|
2018-02-08 18:04:43 +00:00
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#endif /* defined(__arm__) */
|
2018-02-08 18:04:43 +00:00
|
|
|
|
|
|
|
|
#if defined(__alpha__)
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_INIT \
|
2018-02-08 18:04:43 +00:00
|
|
|
asm( \
|
|
|
|
|
"ldq $1, %3 \n\t" \
|
|
|
|
|
"ldq $2, %4 \n\t" \
|
|
|
|
|
"ldq $3, %5 \n\t" \
|
|
|
|
|
"ldq $4, %6 \n\t"
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_CORE \
|
2018-02-08 18:04:43 +00:00
|
|
|
"ldq $6, 0($1) \n\t" \
|
|
|
|
|
"addq $1, 8, $1 \n\t" \
|
|
|
|
|
"mulq $6, $4, $7 \n\t" \
|
|
|
|
|
"umulh $6, $4, $6 \n\t" \
|
|
|
|
|
"addq $7, $3, $7 \n\t" \
|
|
|
|
|
"cmpult $7, $3, $3 \n\t" \
|
|
|
|
|
"ldq $5, 0($2) \n\t" \
|
|
|
|
|
"addq $7, $5, $7 \n\t" \
|
|
|
|
|
"cmpult $7, $5, $5 \n\t" \
|
|
|
|
|
"stq $7, 0($2) \n\t" \
|
|
|
|
|
"addq $2, 8, $2 \n\t" \
|
|
|
|
|
"addq $6, $3, $3 \n\t" \
|
|
|
|
|
"addq $5, $3, $3 \n\t"
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_STOP \
|
2018-02-08 18:04:43 +00:00
|
|
|
"stq $3, %0 \n\t" \
|
|
|
|
|
"stq $2, %1 \n\t" \
|
|
|
|
|
"stq $1, %2 \n\t" \
|
|
|
|
|
: "=m" (c), "=m" (d), "=m" (s) \
|
|
|
|
|
: "m" (s), "m" (d), "m" (c), "m" (b) \
|
|
|
|
|
: "$1", "$2", "$3", "$4", "$5", "$6", "$7" \
|
|
|
|
|
);
|
|
|
|
|
#endif /* Alpha */
|
|
|
|
|
|
|
|
|
|
#if defined(__mips__) && !defined(__mips64)
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_INIT \
|
2018-02-08 18:04:43 +00:00
|
|
|
asm( \
|
|
|
|
|
"lw $10, %3 \n\t" \
|
|
|
|
|
"lw $11, %4 \n\t" \
|
|
|
|
|
"lw $12, %5 \n\t" \
|
|
|
|
|
"lw $13, %6 \n\t"
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_CORE \
|
2018-02-08 18:04:43 +00:00
|
|
|
"lw $14, 0($10) \n\t" \
|
|
|
|
|
"multu $13, $14 \n\t" \
|
|
|
|
|
"addi $10, $10, 4 \n\t" \
|
|
|
|
|
"mflo $14 \n\t" \
|
|
|
|
|
"mfhi $9 \n\t" \
|
|
|
|
|
"addu $14, $12, $14 \n\t" \
|
|
|
|
|
"lw $15, 0($11) \n\t" \
|
|
|
|
|
"sltu $12, $14, $12 \n\t" \
|
|
|
|
|
"addu $15, $14, $15 \n\t" \
|
|
|
|
|
"sltu $14, $15, $14 \n\t" \
|
|
|
|
|
"addu $12, $12, $9 \n\t" \
|
|
|
|
|
"sw $15, 0($11) \n\t" \
|
|
|
|
|
"addu $12, $12, $14 \n\t" \
|
|
|
|
|
"addi $11, $11, 4 \n\t"
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_STOP \
|
2018-02-08 18:04:43 +00:00
|
|
|
"sw $12, %0 \n\t" \
|
|
|
|
|
"sw $11, %1 \n\t" \
|
|
|
|
|
"sw $10, %2 \n\t" \
|
|
|
|
|
: "=m" (c), "=m" (d), "=m" (s) \
|
|
|
|
|
: "m" (s), "m" (d), "m" (c), "m" (b) \
|
2019-07-10 14:15:01 +00:00
|
|
|
: "$9", "$10", "$11", "$12", "$13", "$14", "$15", "lo", "hi" \
|
2018-02-08 18:04:43 +00:00
|
|
|
);
|
|
|
|
|
|
|
|
|
|
#endif /* MIPS */
|
|
|
|
|
#endif /* GNUC */
|
|
|
|
|
|
|
|
|
|
#if (defined(_MSC_VER) && defined(_M_IX86)) || defined(__WATCOMC__)
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_INIT \
|
2018-02-08 18:04:43 +00:00
|
|
|
__asm mov esi, s \
|
|
|
|
|
__asm mov edi, d \
|
|
|
|
|
__asm mov ecx, c \
|
|
|
|
|
__asm mov ebx, b
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_CORE \
|
2018-02-08 18:04:43 +00:00
|
|
|
__asm lodsd \
|
|
|
|
|
__asm mul ebx \
|
|
|
|
|
__asm add eax, ecx \
|
|
|
|
|
__asm adc edx, 0 \
|
|
|
|
|
__asm add eax, [edi] \
|
|
|
|
|
__asm adc edx, 0 \
|
|
|
|
|
__asm mov ecx, edx \
|
|
|
|
|
__asm stosd
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_STOP \
|
|
|
|
|
__asm mov c, ecx \
|
|
|
|
|
__asm mov d, edi \
|
|
|
|
|
__asm mov s, esi
|
|
|
|
|
|
2018-02-08 18:04:43 +00:00
|
|
|
#if defined(MBEDTLS_HAVE_SSE2)
|
|
|
|
|
|
|
|
|
|
#define EMIT __asm _emit
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X8_INIT MULADDC_X1_INIT
|
|
|
|
|
|
|
|
|
|
#define MULADDC_X8_CORE \
|
2018-02-08 18:04:43 +00:00
|
|
|
EMIT 0x0F EMIT 0x6E EMIT 0xC9 \
|
|
|
|
|
EMIT 0x0F EMIT 0x6E EMIT 0xC3 \
|
|
|
|
|
EMIT 0x0F EMIT 0x6E EMIT 0x1F \
|
|
|
|
|
EMIT 0x0F EMIT 0xD4 EMIT 0xCB \
|
|
|
|
|
EMIT 0x0F EMIT 0x6E EMIT 0x16 \
|
|
|
|
|
EMIT 0x0F EMIT 0xF4 EMIT 0xD0 \
|
|
|
|
|
EMIT 0x0F EMIT 0x6E EMIT 0x66 EMIT 0x04 \
|
|
|
|
|
EMIT 0x0F EMIT 0xF4 EMIT 0xE0 \
|
|
|
|
|
EMIT 0x0F EMIT 0x6E EMIT 0x76 EMIT 0x08 \
|
|
|
|
|
EMIT 0x0F EMIT 0xF4 EMIT 0xF0 \
|
|
|
|
|
EMIT 0x0F EMIT 0x6E EMIT 0x7E EMIT 0x0C \
|
|
|
|
|
EMIT 0x0F EMIT 0xF4 EMIT 0xF8 \
|
|
|
|
|
EMIT 0x0F EMIT 0xD4 EMIT 0xCA \
|
|
|
|
|
EMIT 0x0F EMIT 0x6E EMIT 0x5F EMIT 0x04 \
|
|
|
|
|
EMIT 0x0F EMIT 0xD4 EMIT 0xDC \
|
|
|
|
|
EMIT 0x0F EMIT 0x6E EMIT 0x6F EMIT 0x08 \
|
|
|
|
|
EMIT 0x0F EMIT 0xD4 EMIT 0xEE \
|
|
|
|
|
EMIT 0x0F EMIT 0x6E EMIT 0x67 EMIT 0x0C \
|
|
|
|
|
EMIT 0x0F EMIT 0xD4 EMIT 0xFC \
|
|
|
|
|
EMIT 0x0F EMIT 0x7E EMIT 0x0F \
|
|
|
|
|
EMIT 0x0F EMIT 0x6E EMIT 0x56 EMIT 0x10 \
|
|
|
|
|
EMIT 0x0F EMIT 0xF4 EMIT 0xD0 \
|
|
|
|
|
EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \
|
|
|
|
|
EMIT 0x0F EMIT 0x6E EMIT 0x66 EMIT 0x14 \
|
|
|
|
|
EMIT 0x0F EMIT 0xF4 EMIT 0xE0 \
|
|
|
|
|
EMIT 0x0F EMIT 0xD4 EMIT 0xCB \
|
|
|
|
|
EMIT 0x0F EMIT 0x6E EMIT 0x76 EMIT 0x18 \
|
|
|
|
|
EMIT 0x0F EMIT 0xF4 EMIT 0xF0 \
|
|
|
|
|
EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x04 \
|
|
|
|
|
EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \
|
|
|
|
|
EMIT 0x0F EMIT 0x6E EMIT 0x5E EMIT 0x1C \
|
|
|
|
|
EMIT 0x0F EMIT 0xF4 EMIT 0xD8 \
|
|
|
|
|
EMIT 0x0F EMIT 0xD4 EMIT 0xCD \
|
|
|
|
|
EMIT 0x0F EMIT 0x6E EMIT 0x6F EMIT 0x10 \
|
|
|
|
|
EMIT 0x0F EMIT 0xD4 EMIT 0xD5 \
|
|
|
|
|
EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x08 \
|
|
|
|
|
EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \
|
|
|
|
|
EMIT 0x0F EMIT 0xD4 EMIT 0xCF \
|
|
|
|
|
EMIT 0x0F EMIT 0x6E EMIT 0x6F EMIT 0x14 \
|
|
|
|
|
EMIT 0x0F EMIT 0xD4 EMIT 0xE5 \
|
|
|
|
|
EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x0C \
|
|
|
|
|
EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \
|
|
|
|
|
EMIT 0x0F EMIT 0xD4 EMIT 0xCA \
|
|
|
|
|
EMIT 0x0F EMIT 0x6E EMIT 0x6F EMIT 0x18 \
|
|
|
|
|
EMIT 0x0F EMIT 0xD4 EMIT 0xF5 \
|
|
|
|
|
EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x10 \
|
|
|
|
|
EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \
|
|
|
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EMIT 0x0F EMIT 0xD4 EMIT 0xCC \
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EMIT 0x0F EMIT 0x6E EMIT 0x6F EMIT 0x1C \
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EMIT 0x0F EMIT 0xD4 EMIT 0xDD \
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EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x14 \
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EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \
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EMIT 0x0F EMIT 0xD4 EMIT 0xCE \
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EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x18 \
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EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \
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EMIT 0x0F EMIT 0xD4 EMIT 0xCB \
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EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x1C \
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EMIT 0x83 EMIT 0xC7 EMIT 0x20 \
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EMIT 0x83 EMIT 0xC6 EMIT 0x20 \
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EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \
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EMIT 0x0F EMIT 0x7E EMIT 0xC9
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2023-09-25 03:04:06 +00:00
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#define MULADDC_X8_STOP \
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2018-02-08 18:04:43 +00:00
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EMIT 0x0F EMIT 0x77 \
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__asm mov c, ecx \
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__asm mov d, edi \
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2023-09-25 03:04:06 +00:00
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__asm mov s, esi
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2018-02-08 18:04:43 +00:00
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#endif /* SSE2 */
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#endif /* MSVC */
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#endif /* MBEDTLS_HAVE_ASM */
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2023-09-25 03:04:06 +00:00
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#if !defined(MULADDC_X1_CORE)
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2018-02-08 18:04:43 +00:00
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#if defined(MBEDTLS_HAVE_UDBL)
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2023-09-25 03:04:06 +00:00
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#define MULADDC_X1_INIT \
|
2018-02-08 18:04:43 +00:00
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|
{ \
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mbedtls_t_udbl r; \
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mbedtls_mpi_uint r0, r1;
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2023-09-25 03:04:06 +00:00
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#define MULADDC_X1_CORE \
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2018-02-08 18:04:43 +00:00
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r = *(s++) * (mbedtls_t_udbl) b; \
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r0 = (mbedtls_mpi_uint) r; \
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r1 = (mbedtls_mpi_uint)( r >> biL ); \
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r0 += c; r1 += (r0 < c); \
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r0 += *d; r1 += (r0 < *d); \
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c = r1; *(d++) = r0;
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|
2023-09-25 03:04:06 +00:00
|
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|
#define MULADDC_X1_STOP \
|
2018-02-08 18:04:43 +00:00
|
|
|
}
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|
2023-09-25 03:04:06 +00:00
|
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|
#else /* MBEDTLS_HAVE_UDBL */
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|
|
#define MULADDC_X1_INIT \
|
2018-02-08 18:04:43 +00:00
|
|
|
{ \
|
|
|
|
|
mbedtls_mpi_uint s0, s1, b0, b1; \
|
|
|
|
|
mbedtls_mpi_uint r0, r1, rx, ry; \
|
|
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|
b0 = ( b << biH ) >> biH; \
|
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|
b1 = ( b >> biH );
|
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|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_CORE \
|
2018-02-08 18:04:43 +00:00
|
|
|
s0 = ( *s << biH ) >> biH; \
|
|
|
|
|
s1 = ( *s >> biH ); s++; \
|
|
|
|
|
rx = s0 * b1; r0 = s0 * b0; \
|
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|
|
ry = s1 * b0; r1 = s1 * b1; \
|
|
|
|
|
r1 += ( rx >> biH ); \
|
|
|
|
|
r1 += ( ry >> biH ); \
|
|
|
|
|
rx <<= biH; ry <<= biH; \
|
|
|
|
|
r0 += rx; r1 += (r0 < rx); \
|
|
|
|
|
r0 += ry; r1 += (r0 < ry); \
|
|
|
|
|
r0 += c; r1 += (r0 < c); \
|
|
|
|
|
r0 += *d; r1 += (r0 < *d); \
|
|
|
|
|
c = r1; *(d++) = r0;
|
|
|
|
|
|
2023-09-25 03:04:06 +00:00
|
|
|
#define MULADDC_X1_STOP \
|
2018-02-08 18:04:43 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#endif /* C (longlong) */
|
2023-09-25 03:04:06 +00:00
|
|
|
#endif /* C (generic) */
|
|
|
|
|
|
|
|
|
|
#if !defined(MULADDC_X2_CORE)
|
|
|
|
|
#define MULADDC_X2_INIT MULADDC_X1_INIT
|
|
|
|
|
#define MULADDC_X2_STOP MULADDC_X1_STOP
|
|
|
|
|
#define MULADDC_X2_CORE MULADDC_X1_CORE MULADDC_X1_CORE
|
|
|
|
|
#endif /* MULADDC_X2_CORE */
|
|
|
|
|
|
|
|
|
|
#if !defined(MULADDC_X4_CORE)
|
|
|
|
|
#define MULADDC_X4_INIT MULADDC_X2_INIT
|
|
|
|
|
#define MULADDC_X4_STOP MULADDC_X2_STOP
|
|
|
|
|
#define MULADDC_X4_CORE MULADDC_X2_CORE MULADDC_X2_CORE
|
|
|
|
|
#endif /* MULADDC_X4_CORE */
|
|
|
|
|
|
|
|
|
|
#if !defined(MULADDC_X8_CORE)
|
|
|
|
|
#define MULADDC_X8_INIT MULADDC_X4_INIT
|
|
|
|
|
#define MULADDC_X8_STOP MULADDC_X4_STOP
|
|
|
|
|
#define MULADDC_X8_CORE MULADDC_X4_CORE MULADDC_X4_CORE
|
|
|
|
|
#endif /* MULADDC_X8_CORE */
|
2018-02-08 18:04:43 +00:00
|
|
|
|
2023-04-18 08:38:24 +00:00
|
|
|
/* *INDENT-ON* */
|
2018-02-08 18:04:43 +00:00
|
|
|
#endif /* bn_mul.h */
|
