550 lines
13 KiB
C++
550 lines
13 KiB
C++
// Copyright 2009-2021 Intel Corporation
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// SPDX-License-Identifier: Apache-2.0
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#pragma once
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#include "platform.h"
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#if defined(__WIN32__)
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#include <intrin.h>
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#endif
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#if defined(__ARM_NEON)
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#include "../simd/arm/emulation.h"
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#else
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#include <immintrin.h>
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#if defined(__EMSCRIPTEN__)
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#include "../simd/wasm/emulation.h"
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#endif
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#endif
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#if defined(__BMI__) && defined(__GNUC__) && !defined(__INTEL_COMPILER)
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#if !defined(_tzcnt_u32)
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#define _tzcnt_u32 __tzcnt_u32
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#endif
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#if !defined(_tzcnt_u64)
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#define _tzcnt_u64 __tzcnt_u64
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#endif
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#endif
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#if defined(__aarch64__)
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#if !defined(_lzcnt_u32)
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#define _lzcnt_u32 __builtin_clz
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#endif
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#else
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#if defined(__LZCNT__)
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#if !defined(_lzcnt_u32)
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#define _lzcnt_u32 __lzcnt32
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#endif
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#if !defined(_lzcnt_u64)
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#define _lzcnt_u64 __lzcnt64
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#endif
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#endif
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#endif
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#if defined(__WIN32__)
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# if !defined(NOMINMAX)
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# define NOMINMAX
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# endif
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# include <windows.h>
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#endif
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/* normally defined in pmmintrin.h, but we always need this */
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#if !defined(_MM_SET_DENORMALS_ZERO_MODE)
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#define _MM_DENORMALS_ZERO_ON (0x0040)
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#define _MM_DENORMALS_ZERO_OFF (0x0000)
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#define _MM_DENORMALS_ZERO_MASK (0x0040)
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#define _MM_SET_DENORMALS_ZERO_MODE(x) (_mm_setcsr((_mm_getcsr() & ~_MM_DENORMALS_ZERO_MASK) | (x)))
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#endif
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namespace embree
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{
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////////////////////////////////////////////////////////////////////////////////
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/// Windows Platform
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////////////////////////////////////////////////////////////////////////////////
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#if defined(__WIN32__)
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__forceinline size_t read_tsc()
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{
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LARGE_INTEGER li;
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QueryPerformanceCounter(&li);
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return (size_t)li.QuadPart;
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}
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__forceinline int bsf(int v) {
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#if defined(__AVX2__) && !defined(__aarch64__)
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return _tzcnt_u32(v);
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#else
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unsigned long r = 0; _BitScanForward(&r,v); return r;
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#endif
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}
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__forceinline unsigned bsf(unsigned v) {
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#if defined(__AVX2__) && !defined(__aarch64__)
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return _tzcnt_u32(v);
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#else
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unsigned long r = 0; _BitScanForward(&r,v); return r;
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#endif
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}
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#if defined(__X86_64__)
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__forceinline size_t bsf(size_t v) {
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#if defined(__AVX2__)
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return _tzcnt_u64(v);
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#else
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unsigned long r = 0; _BitScanForward64(&r,v); return r;
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#endif
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}
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#endif
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__forceinline int bscf(int& v)
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{
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int i = bsf(v);
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v &= v-1;
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return i;
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}
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__forceinline unsigned bscf(unsigned& v)
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{
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unsigned i = bsf(v);
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v &= v-1;
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return i;
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}
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#if defined(__X86_64__)
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__forceinline size_t bscf(size_t& v)
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{
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size_t i = bsf(v);
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v &= v-1;
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return i;
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}
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#endif
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__forceinline int bsr(int v) {
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#if defined(__AVX2__) && !defined(__aarch64__)
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return 31 - _lzcnt_u32(v);
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#else
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unsigned long r = 0; _BitScanReverse(&r,v); return r;
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#endif
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}
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__forceinline unsigned bsr(unsigned v) {
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#if defined(__AVX2__) && !defined(__aarch64__)
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return 31 - _lzcnt_u32(v);
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#else
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unsigned long r = 0; _BitScanReverse(&r,v); return r;
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#endif
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}
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#if defined(__X86_64__)
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__forceinline size_t bsr(size_t v) {
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#if defined(__AVX2__)
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return 63 -_lzcnt_u64(v);
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#else
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unsigned long r = 0; _BitScanReverse64(&r, v); return r;
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#endif
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}
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#endif
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__forceinline int lzcnt(const int x)
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{
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#if defined(__AVX2__) && !defined(__aarch64__)
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return _lzcnt_u32(x);
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#else
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if (unlikely(x == 0)) return 32;
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return 31 - bsr(x);
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#endif
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}
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__forceinline int btc(int v, int i) {
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long r = v; _bittestandcomplement(&r,i); return r;
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}
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__forceinline int bts(int v, int i) {
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long r = v; _bittestandset(&r,i); return r;
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}
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__forceinline int btr(int v, int i) {
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long r = v; _bittestandreset(&r,i); return r;
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}
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#if defined(__X86_64__)
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__forceinline size_t btc(size_t v, size_t i) {
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size_t r = v; _bittestandcomplement64((__int64*)&r,i); return r;
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}
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__forceinline size_t bts(size_t v, size_t i) {
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__int64 r = v; _bittestandset64(&r,i); return r;
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}
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__forceinline size_t btr(size_t v, size_t i) {
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__int64 r = v; _bittestandreset64(&r,i); return r;
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}
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#endif
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__forceinline int32_t atomic_cmpxchg(volatile int32_t* p, const int32_t c, const int32_t v) {
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return _InterlockedCompareExchange((volatile long*)p,v,c);
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}
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////////////////////////////////////////////////////////////////////////////////
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/// Unix Platform
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////////////////////////////////////////////////////////////////////////////////
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#else
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#if defined(__i386__) && defined(__PIC__)
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__forceinline void __cpuid(int out[4], int op)
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{
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asm volatile ("xchg{l}\t{%%}ebx, %1\n\t"
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"cpuid\n\t"
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"xchg{l}\t{%%}ebx, %1\n\t"
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: "=a"(out[0]), "=r"(out[1]), "=c"(out[2]), "=d"(out[3])
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: "0"(op));
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}
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__forceinline void __cpuid_count(int out[4], int op1, int op2)
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{
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asm volatile ("xchg{l}\t{%%}ebx, %1\n\t"
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"cpuid\n\t"
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"xchg{l}\t{%%}ebx, %1\n\t"
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: "=a" (out[0]), "=r" (out[1]), "=c" (out[2]), "=d" (out[3])
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: "0" (op1), "2" (op2));
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}
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#elif defined(__X86_ASM__)
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__forceinline void __cpuid(int out[4], int op) {
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#if defined(__ARM_NEON)
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if (op == 0) { // Get CPU name
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out[0] = 0x41524d20;
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out[1] = 0x41524d20;
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out[2] = 0x41524d20;
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out[3] = 0x41524d20;
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}
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#else
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asm volatile ("cpuid" : "=a"(out[0]), "=b"(out[1]), "=c"(out[2]), "=d"(out[3]) : "a"(op));
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#endif
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}
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#if !defined(__ARM_NEON)
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__forceinline void __cpuid_count(int out[4], int op1, int op2) {
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asm volatile ("cpuid" : "=a"(out[0]), "=b"(out[1]), "=c"(out[2]), "=d"(out[3]) : "a"(op1), "c"(op2));
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}
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#endif
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#endif
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__forceinline uint64_t read_tsc() {
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#if defined(__X86_ASM__)
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uint32_t high,low;
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asm volatile ("rdtsc" : "=d"(high), "=a"(low));
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return (((uint64_t)high) << 32) + (uint64_t)low;
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#else
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/* Not supported yet, meaning measuring traversal cost per pixel does not work. */
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return 0;
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#endif
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}
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__forceinline int bsf(int v) {
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#if defined(__ARM_NEON)
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return __builtin_ctz(v);
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#else
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#if defined(__AVX2__)
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return _tzcnt_u32(v);
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#elif defined(__X86_ASM__)
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int r = 0; asm ("bsf %1,%0" : "=r"(r) : "r"(v)); return r;
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#else
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return __builtin_ctz(v);
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#endif
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#endif
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}
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#if defined(__64BIT__)
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__forceinline unsigned bsf(unsigned v)
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{
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#if defined(__ARM_NEON)
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return __builtin_ctz(v);
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#else
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#if defined(__AVX2__)
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return _tzcnt_u32(v);
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#elif defined(__X86_ASM__)
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unsigned r = 0; asm ("bsf %1,%0" : "=r"(r) : "r"(v)); return r;
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#else
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return __builtin_ctz(v);
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#endif
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#endif
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}
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#endif
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__forceinline size_t bsf(size_t v) {
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#if defined(__AVX2__) && !defined(__aarch64__)
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#if defined(__X86_64__)
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return _tzcnt_u64(v);
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#else
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return _tzcnt_u32(v);
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#endif
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#elif defined(__X86_ASM__)
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size_t r = 0; asm ("bsf %1,%0" : "=r"(r) : "r"(v)); return r;
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#else
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return __builtin_ctzl(v);
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#endif
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}
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__forceinline int bscf(int& v)
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{
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int i = bsf(v);
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v &= v-1;
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return i;
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}
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#if defined(__64BIT__)
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__forceinline unsigned int bscf(unsigned int& v)
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{
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unsigned int i = bsf(v);
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v &= v-1;
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return i;
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}
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#endif
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__forceinline size_t bscf(size_t& v)
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{
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size_t i = bsf(v);
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v &= v-1;
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return i;
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}
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__forceinline int bsr(int v) {
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#if defined(__AVX2__) && !defined(__aarch64__)
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return 31 - _lzcnt_u32(v);
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#elif defined(__X86_ASM__)
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int r = 0; asm ("bsr %1,%0" : "=r"(r) : "r"(v)); return r;
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#else
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return __builtin_clz(v) ^ 31;
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#endif
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}
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#if defined(__64BIT__) || defined(__EMSCRIPTEN__)
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__forceinline unsigned bsr(unsigned v) {
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#if defined(__AVX2__)
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return 31 - _lzcnt_u32(v);
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#elif defined(__X86_ASM__)
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unsigned r = 0; asm ("bsr %1,%0" : "=r"(r) : "r"(v)); return r;
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#else
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return __builtin_clz(v) ^ 31;
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#endif
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}
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#endif
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__forceinline size_t bsr(size_t v) {
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#if defined(__AVX2__) && !defined(__aarch64__)
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#if defined(__X86_64__)
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return 63 - _lzcnt_u64(v);
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#else
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return 31 - _lzcnt_u32(v);
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#endif
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#elif defined(__X86_ASM__)
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size_t r = 0; asm ("bsr %1,%0" : "=r"(r) : "r"(v)); return r;
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#else
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return (sizeof(v) * 8 - 1) - __builtin_clzl(v);
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#endif
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}
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__forceinline int lzcnt(const int x)
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{
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#if defined(__AVX2__) && !defined(__aarch64__)
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return _lzcnt_u32(x);
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#else
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if (unlikely(x == 0)) return 32;
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return 31 - bsr(x);
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#endif
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}
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__forceinline size_t blsr(size_t v) {
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#if defined(__AVX2__) && !defined(__aarch64__)
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#if defined(__INTEL_COMPILER)
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return _blsr_u64(v);
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#else
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#if defined(__X86_64__)
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return __blsr_u64(v);
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#else
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return __blsr_u32(v);
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#endif
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#endif
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#else
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return v & (v-1);
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#endif
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}
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__forceinline int btc(int v, int i) {
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#if defined(__X86_ASM__)
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int r = 0; asm ("btc %1,%0" : "=r"(r) : "r"(i), "0"(v) : "flags" ); return r;
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#else
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return (v ^ (1 << i));
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#endif
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}
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__forceinline int bts(int v, int i) {
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#if defined(__X86_ASM__)
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int r = 0; asm ("bts %1,%0" : "=r"(r) : "r"(i), "0"(v) : "flags"); return r;
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#else
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return (v | (1 << i));
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#endif
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}
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__forceinline int btr(int v, int i) {
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#if defined(__X86_ASM__)
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int r = 0; asm ("btr %1,%0" : "=r"(r) : "r"(i), "0"(v) : "flags"); return r;
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#else
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return (v & ~(1 << i));
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#endif
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}
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__forceinline size_t btc(size_t v, size_t i) {
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#if defined(__X86_ASM__)
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size_t r = 0; asm ("btc %1,%0" : "=r"(r) : "r"(i), "0"(v) : "flags" ); return r;
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#else
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return (v ^ (1 << i));
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#endif
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}
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__forceinline size_t bts(size_t v, size_t i) {
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#if defined(__X86_ASM__)
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size_t r = 0; asm ("bts %1,%0" : "=r"(r) : "r"(i), "0"(v) : "flags"); return r;
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#else
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return (v | (1 << i));
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#endif
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}
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__forceinline size_t btr(size_t v, size_t i) {
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#if defined(__X86_ASM__)
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size_t r = 0; asm ("btr %1,%0" : "=r"(r) : "r"(i), "0"(v) : "flags"); return r;
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#else
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return (v & ~(1 << i));
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#endif
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}
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__forceinline int32_t atomic_cmpxchg(int32_t volatile* value, int32_t comparand, const int32_t input) {
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return __sync_val_compare_and_swap(value, comparand, input);
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}
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#endif
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////////////////////////////////////////////////////////////////////////////////
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/// All Platforms
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////////////////////////////////////////////////////////////////////////////////
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#if defined(__clang__) || defined(__GNUC__)
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#if !defined(_mm_undefined_ps)
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__forceinline __m128 _mm_undefined_ps() { return _mm_setzero_ps(); }
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#endif
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#if !defined(_mm_undefined_si128)
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__forceinline __m128i _mm_undefined_si128() { return _mm_setzero_si128(); }
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#endif
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#if !defined(_mm256_undefined_ps) && defined(__AVX__)
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__forceinline __m256 _mm256_undefined_ps() { return _mm256_setzero_ps(); }
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#endif
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#if !defined(_mm256_undefined_si256) && defined(__AVX__)
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__forceinline __m256i _mm256_undefined_si256() { return _mm256_setzero_si256(); }
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#endif
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#if !defined(_mm512_undefined_ps) && defined(__AVX512F__)
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__forceinline __m512 _mm512_undefined_ps() { return _mm512_setzero_ps(); }
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#endif
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#if !defined(_mm512_undefined_epi32) && defined(__AVX512F__)
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__forceinline __m512i _mm512_undefined_epi32() { return _mm512_setzero_si512(); }
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#endif
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#endif
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#if defined(__SSE4_2__) || defined(__ARM_NEON)
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__forceinline int popcnt(int in) {
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return _mm_popcnt_u32(in);
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}
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__forceinline unsigned popcnt(unsigned in) {
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return _mm_popcnt_u32(in);
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}
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#if defined(__64BIT__)
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__forceinline size_t popcnt(size_t in) {
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return _mm_popcnt_u64(in);
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}
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#endif
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#endif
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#if defined(__X86_ASM__)
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__forceinline uint64_t rdtsc()
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{
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int dummy[4];
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__cpuid(dummy,0);
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uint64_t clock = read_tsc();
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__cpuid(dummy,0);
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return clock;
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}
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#endif
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__forceinline void pause_cpu(const size_t N = 8)
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{
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for (size_t i=0; i<N; i++)
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_mm_pause();
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}
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/* prefetches */
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__forceinline void prefetchL1 (const void* ptr) { _mm_prefetch((const char*)ptr,_MM_HINT_T0); }
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__forceinline void prefetchL2 (const void* ptr) { _mm_prefetch((const char*)ptr,_MM_HINT_T1); }
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__forceinline void prefetchL3 (const void* ptr) { _mm_prefetch((const char*)ptr,_MM_HINT_T2); }
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__forceinline void prefetchNTA(const void* ptr) { _mm_prefetch((const char*)ptr,_MM_HINT_NTA); }
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__forceinline void prefetchEX (const void* ptr) {
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#if defined(__INTEL_COMPILER)
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_mm_prefetch((const char*)ptr,_MM_HINT_ET0);
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#else
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_mm_prefetch((const char*)ptr,_MM_HINT_T0);
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#endif
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}
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__forceinline void prefetchL1EX(const void* ptr) {
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prefetchEX(ptr);
|
|
}
|
|
|
|
__forceinline void prefetchL2EX(const void* ptr) {
|
|
prefetchEX(ptr);
|
|
}
|
|
#if defined(__AVX2__) && !defined(__aarch64__)
|
|
__forceinline unsigned int pext(unsigned int a, unsigned int b) { return _pext_u32(a, b); }
|
|
__forceinline unsigned int pdep(unsigned int a, unsigned int b) { return _pdep_u32(a, b); }
|
|
#if defined(__X86_64__)
|
|
__forceinline size_t pext(size_t a, size_t b) { return _pext_u64(a, b); }
|
|
__forceinline size_t pdep(size_t a, size_t b) { return _pdep_u64(a, b); }
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(__AVX512F__)
|
|
#if defined(__INTEL_COMPILER)
|
|
__forceinline float mm512_cvtss_f32(__m512 v) {
|
|
return _mm512_cvtss_f32(v);
|
|
}
|
|
__forceinline int mm512_mask2int(__mmask16 k1) {
|
|
return _mm512_mask2int(k1);
|
|
}
|
|
__forceinline __mmask16 mm512_int2mask(int mask) {
|
|
return _mm512_int2mask(mask);
|
|
}
|
|
#else
|
|
__forceinline float mm512_cvtss_f32(__m512 v) { // FIXME: _mm512_cvtss_f32 neither supported by clang v4.0.0 nor GCC 6.3
|
|
return _mm_cvtss_f32(_mm512_castps512_ps128(v));
|
|
}
|
|
__forceinline int mm512_mask2int(__mmask16 k1) { // FIXME: _mm512_mask2int not yet supported by GCC 6.3
|
|
return (int)k1;
|
|
}
|
|
__forceinline __mmask16 mm512_int2mask(int mask) { // FIXME: _mm512_int2mask not yet supported by GCC 6.3
|
|
return (__mmask16)mask;
|
|
}
|
|
#endif
|
|
#endif
|
|
}
|